1. Field of the Invention
This invention relates in general to electronic circuit modules, and, more particularly, to improved means and methods for providing high density circuit assemblies and modules having a multiplicity of interconnected integrated circuit chips or other components.
2. Background Art
Modern fabrication techniques make it possible to pack very large numbers of high speed semiconductor devices into individual integrated circuit (IC) chips or die. However, in order to build functioning systems, the individual ICs must be electrically interconnected in some way. Historically this has been done by mounting the individual IC die in sealed packages. These sealed packages protect the die from the environment and provide rugged external leads or pads which can be used for interconnecting the ICs in the system. The packaged die are generally mounted by their leads on a circuit board which contains the interconnect wiring. The circuit board often has multiple layers of interconnect wiring and may be fabricated of metallized plastics, ceramics, or impregnated paper or fabric. A significant disadvantage of this method is that the wiring length from die to die, through the individual packages and along the conductors of the circuit board, is many times the size of the IC die. With very high speed devices, these comparatively long wiring lengths cause significant propagation delays, reducing the overall system performance.
More recently, it has been possible to produce IC die which are themselves hermetically sealed so that they may be mounted directly on the circuit board or substrate rather than being housed in individual packages. The circuit board or assembly is then encapsulated as a whole to form a module. Omitting the individual packages permits the die to be closer together, thus reducing the propagation delay in the circuit board. While this provides some improvement, it does not completely solve the problem of excess propagation delay. Further, severe problems having to do with reliability and with removing heat still remain.
The IC die or chips have bonding pads which are connected to the wiring pattern on the circuit board by a variety of off-chip connection means, generally involving soldering or welding. Examples are wire bonds, flexible tapes, beam leads, and solder bumps. A significant difficulty with these prior art approaches is that in most cases the metallurgy needed to make such off-chip connections is different than the metallurgy used for the on-chip interconnections within the IC chip. It is well known that the reliability of off-chip interconnections is substantially poorer than the reliability of on-chip interconnections. Further, these prior art off-chip connections utilize much more area on the circuit board or substrate than is desired. This contributes to the comparatively low packing density of prior art circuit modules, even when the individual die packages are omitted, and the continued significant propagation delays associated therewith.
Prior art modules have utilized materials having markedly different coefficients of thermal expansions. As a consequence thermal stresses are induced during temperature cycling. This further degrades reliability of the finished modules. Additionally, prior art modules have not provided simple and effective means for removal of heat from the many IC chips or other components within the module. Thus, a need continues to exist for improved modules for integrated circuits and other components, particularly high density modules, having improved packing density, propagation delay, heat dissipation, ease of manufacture, and cost.
Accordingly, it is an object of the present invention to provide an improved means and method for electronic modules for integrated circuits having a high packing density.
It is a further object of the present invention to provide an improved means and method for electronic modules wherein the number of welded or soldered joints required to interconnect the IC chips or other components within the module is reduced.
It is an additional object of the present invention to provide an improved means and method for electronic modules wherein the generation of mechanical stress from temperature changes is reduced.
It is a further object of the present invention to provide an improved means and method for electronic modules wherein the materials used for the module comprise the same material as used for the integrated circuit chip.
It is an additional object of the present invention to provide an improved means and method for electronic modules wherein the principle elements of the module are self aligning for easy assembly.
It is a further object of the present invention to provide an improved means and method for electronic modules wherein the individual IC chips are mounted in a supporting member so as to have accessible rear faces adapted for contacting a planar heat sink, and exposed front faces which are smoothly joined to, and optimally, part of the interconnect wiring surface.
It is an additional object of the present invention to provide an arrangement for including semiconductor die prepared using different processing technologies (e.g. TTL, NMOS, linear, ECL, etc.) within the same monolithic substrate.
It is a further object of the present invention to provide a means and method for incorporating pretested die in a monolithic substrate which can be interconnected using planar metallization technology.